Job Description
Our Client:
Our client is a newly established firm in Asia that is looking to build a strong presence in the automotive and Ethernet Industry. They are seeking for a PLL Design Engineer to be a part of their team.
The Responsobilities:
* Develop building blocks for PLL, DLL, and clock distribution, among other things
* Collaborate closely with the mask design team to create a layout view of designs
* Conduct top-level spice and mixed-mode simulations to confirm that the integration is correct
* Analyze ATE and lab test results to identify issues that affect yield and implement solutions to fix them
* Collaborate with system teams during system bring up and debugging
The Requirements:
* Experience designing mixed-signal circuit building blocks for high-speed interfaces, such as PLL, DLL, and clock distribution
* Knowledge of VCO design, including ring VCOs and LC VCOs
* Good understanding of bandgaps, bias, op-amps, LDOs, feedback and compensation techniques, as well as digitally assisted analog circuit techniques
* Ability to guide mask designers on schematic layouts and perform post-layout simulations
* Skills in pre-layout and post-layout design optimization to meet specifications in tests such as PVT, sensitivity, aging, and electromigration simulation
* Ability to create lab and ATE test plans and measurements for characterization and volume production
For a more confidential discussion, please feel free to contact Mary Das at mary.das@rgf-professional.com
Disclaimer: The Company complies with the Tripartite Guidelines on Fair Employment Practices (TGFEP), including the prevailing guidelines on recruitment. All qualified applicants will be considered for the position regardless of their age, race, religion, nationality, marital status, or family responsibilities. A more detailed discussion of the TGFEP is available on the Tripartite Alliance for Fair and Progressive Employment Practices (TAFEP) website at https://www.tal.sg/tafep.